EE295 - ASIC Design With VHDL Class - Fall 2003

Prepared By: James Swift,

•  Senior Engineer, EDA Laboratory, IBM Microelectronic Division;
• http://w3.btv.ibm.com/~jswift/uvm_class

• Visiting Lecturer, University of Vermont - College of Engineering
• http://www.emba.uvm.edu/~jswift/uvm_class

Description:

To Reach Me

• office hours : Call for appointment
• phone: 802-769-6490 (W) -7226 (FAX) 434-2880 (H)
• email  Internet : jswift@us.ibm.com
• Class Mail List Archive
• E-Mail List Server Commands to  listserv@list.uvm.edu
• command list_name | arguments |
• For Example:
• subscribe vhdl <students_e-mail_address>  - receive e-mail of all future postings
• index vhdl - list of what's there
• get vhdl file_name - get something
• unsubscribe vhdl  or signoffvhdl  - to discontinue receiving postings
• E-Mail Messages Sent to vhdl@list.uvm.edu Are Received by the Subscribers ( the Class )

Distance Learning Guidelines:

• Identify your site technician
• We need a student volunteer to aim the camera & ELMO tablet
• Camera remains on last active station, in order to ask questions or make statements it is necessary for you to
• announce yourself first  "Professor Swift this is Joe at IBM.."  ( pause )
• I'll acknowledge " Go ahead Joe.."
• By then I should have the IBM classroom on my monitor and our volunteer has you in camera's view
• Easy on the extraneous noises
• If video is unavailable audio line is available 800-529-7730 ( 6 lines max )
• VHS copies are available. Contact me before the class.
  

Required Text:

 'The Designer's Guide to VHDL', Peter Ashenden,

Morgan-Kaufman Publishers

Paperback - 668 pages (December 1995)Morgan Kaufman Publishers;

ISBN: 1558602704 ; Dimensions (in inches): 1.28 x 9.32 x 7.42

Required Text:

'Application-Specific Integrated Circuits'

Michael John Sebastian Smith
Addison-Wesley Publishing Company
VLSI Design Series
1040 pages
ISBN 0-201-50022-1
June 1997

---

Prerequisites:

• UVM EE131 Fundamentals of Digital Design or equiv. Logic Design Course
• UVM CS21 or CS26 Computer Programming or equiv. C Programming Course
• Unix Literate ( for IBM and UVM Lab Sections ):
• Must have Student Account or Access to IBM AFS Facility
• log in
• editing files, running scripts, modifying environmental variables, making directories
• e-mail
• access to web browser with hard copy capability
• NT Literate ( for BF Goodrich Sections )

Grading Policy

• 25% Project Consisting of:
• Description
• VHDL
• Verification Suite/Delay Report
• EDIF Netlist
• 75%
• Homework = Reading + 4 Problem Sets
• XX Labs:
• Absence Policy:
• Full Attendance Expected at Tuesday Lectures
• Don't Miss More Than 4
• Thursday Labs - Attendance Optional - Preferred for Consultations
• Office Hours:
• No Scheduled Hours
• Contact Me for Campus Meeting

Project

• Form Work Teams of 2 - 4 People
• Based on DLX from Ch 15 of the Text - Begin Reading Chapter 15 Now
• Your Free to Define an ASIC Project of Your Own - It Must be Original
• Your Own ASIC Must Have a Description Submitted for Approval Before MidTerm
• Design Should Contain a State Machine and a Algorithmic Macro(s) ( e.g. Counter, Adder, etc. ) and demonstrate a variety of coding styles
• You Must Simulate the Major Macros in Your Design
• You Must Synthesize At Least One Macro In Your Design

Course Outline:

• 1.0 What is an ASIC?
• 1.1 Types of ASICs
• 1.1.1 Standard-Cell-Based ASICs
• 1.1.2 Gate-Array_based ASICs
• 1.1.3 Channeled Gate Array
• 1.1.4 Structured Gate Array
• 1.1.5 Programmable Logic Devices
• 1.1.6 Field Programmable Gate Arrays
• 1.2 Design Flow
• 1.4 Economics of ASICs
• 1.5 ASIC Cell Libraries
• Figures for Ch 1
• IntroductionRead Chap 1
• Modeling Digital Systems
• Modeling Domains
• What is VHDL?
• History of VHDL
• Reballoting the Standard - 1076-87 vs -93
• Some Useful VHDL Web Resources
• More Resources
• What is an ASIC?
•  What is a Design Methodology
• VHDL Overview:
• Modeling Domains
• VHDL Modeling Concepts
• Test Benches
• Analysis, Elaboration and Execution
• Lexical Elements
• Comments
• Identifiers
• Numbers
• Characters
• Entity / Architecture
• Package / Library / Use
• Process
• Scalar Types - Read Chap 2
• Data Objects
• Constant
• Variable
• Scalar Types
• Type Declarations
• The Predefined Package Standard  ( Appendix B )
• Discrete Types:
• Integer
• Floating Point ( Real )
• Physical Types
• Enumerated Types
• Type Classification
• Attributes
• Expressions
• Sequential Statements - Read Chap 3
• What is Sequential Processing
• Signal Evaluation vs Variable Assignment
• Signal Assignment Within a Process
• The Process Statement
• The Assert Statement
• Sequential Statements:
• If
• Case
• Null
• Loop
• Next/Exit
• Wait
• Return
• Composite Data Types and Operations - Read Chap 4
• Arrays
• Examples of Array Declarations
• Multidimensional
• Array Aggregates
• Array Attributes
• Unconstrained Array Types
• Examples of Unconstrained Vectors: Strings, Bit_Vectors, Std_ULogic_Vector
• Unconstrained Array Ports
• Array Operations
•  Defined
•  Boolean
•  Shift
•  Relational
•  Concatenation
• Array Slices
• Record
• Example
• Basic Modeling Constructs - Read Chap 5
• Entity Declarations
• Architecture Bodies
• Concurrent Statements
• Signal Declarations
• Behavioral Descriptions
• Signal Assignment
• Signal Attributes
• Delta Delay
• Delay Mechanisms
• Process Statements
• Wait Statements
• Concurrent Signal Assignment
• Concurrent Assert Statements
• Passive Processes
• Structural Descriptions
• Component Instantiation and Port Maps
• Design Processing
• Analysis
• Design Libraries
• ASIC Methodology - Read Chap 1 of HDL Chip Design & "Design Methodology for IBM ASIC Products"
• Example Methodology
• Design Steps
• Project Definition
• Design Capture
• Simulation
• Synthesis
• Verification
• Test
• Physical Design
• Subprograms & Packages - Read Chap 7 & 8
• Procedures
• Procedure Parameters
• Signal Parameters
• Default Values
• Unconstrained Array Parameters
• Functions
• Pure And Impure Functions
• FunctionNow
• Overloading
• Conversion Function
• Package Declarations
• Package Body

 
• Aliases - Read Chap 9
• Aliases for Data Objects
• Aliases for Non-Data Objects
• Resolved Signals - Read Chap 11
• Basic Resolved Signals
• Resolution Functions
• IEEE Std_Logic_1164 Resolved Subtypes
• Resolved Signals and Ports
• Generic Signals - Read Chap 12
• Parameterizing Behavior
• Parameterizing Structure
• Components and Configuration - Read Chap 13
• Components
• Component Instantiation
• Packaging Components
• Configuration
• The Default Configuration
• Configuring
• Components
• Ports
• Generics in
• Default Specification
• Component Instantiation
• Configuration
• Blocks
• Architectures
• Generate Statements - Read Chap 14
• Simple Iterative Generate
• Conditionally Executed Generate
• Recursive Generate
• Configuration of a Generate Statement
• Guards and Blocks - Read Chap 16
• NormalSignals
• Disconnection
• Guarded Signals
• bus signals
• register signals
•  GuardedSignal Assignments
• Keyword null
• Composite guarded signals
• 'Driving Attribute
• Guarded Ports & Procedure Arguments
• Blocks
• Guarded Blocks
• Access Types and Abstract Data Types - Read Chap 17
• Access Types
• Type Declarations
• Using an Access Type
• procedure READLINE
• Linked Lists
• Type Declarations:
• Building a Linked List
• Files and I/O - Read Chap 18
• File Declarations
• Reading from Files
• Writing to Files
• Explicit Open and Close
• File I/O Status
• Files Declared in SubPrograms
• Text I/O
• Types
• PreDefined Files
• Read Procedures
• Write Procedures:
• Detecting End of File
•  Example of TextIO Read
•  Example of TextIO Write
• Attributes and Groups - Read Chap 20
• Predefined Attributes
•  Attributes of Scalar Types
• VHDL-93 Attributes of Scalar Types
•  Attributes of Array Types
•  VHDL-93 Attributes of Array Types
•  Attributes of Signals - Signal
•  Attributes for Signals - Variable
• User Defined Attributes
•  Declaration of
•  Specification
•  Attach to entity_class
• VHDL-93  Attribute entity_class
• Using Attributes
• Signatures
• Use of others | all
• VHDL-93 Attribute Foreign
• VHDL-93 Groups
• Declaration of a Group
• Using a Group
• Logic Synthesis
• Synthesis
  
• Simulation and Verification
• Test

• Synthesis Survey - Technology Mapping, Logic Optimization, Delay Calculation, Area/Performance Trade Off, New IEEE Package, Common Problems Clock Networks
• IEEE 1076-1993 Updates to the VHDL Language Standard -
• Test Survey
• Physical Synthesis
• Power Compiler

Labs:

Roster - see prof