Lab 1: Event-Driven Simulation: Set Up

1) How Synopsys' VCS Simulator Works

The following commands are used to develop VHDL designs using V-System:

• vhdlan
• scs
• scsim
• scirocco
  
  

2) Finding Synopsys' VCS Simulator Installation

V-System is installed at several IBM sites or availaible from MTI's FTP Server.

IBM Burlington

/afs/btv/data/uvm_class/scirocco2002.12.1

University of Vermont

~jswift/uvm_class/scirocco2002.12.1




  

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3) Synopsys' VCS Simulator Documents

Useful V-System Documents ( all in Adobe PDF Format ):
• Release Notes
  
  
• VHDL Simulation
  Quick Reference         <<-- You'll want to refer to this as you perform the lab
  
  
• VHDL Simulation
  User Guide
  
  
• VHDL Simulation
  Coding and Modeling
  Style Guide
  
  
• Scirocco-i
  Quick Reference
  
  
• Scirocco-i 
  User Guide

4) Example VHDL

• gates.vhd     
• adder.vhd    
• testadder.vhd 

5) Exercise: Setting Up VCS

You'll need to log into a workstation, modify some script files, create directories and finally execute the v-system commands described above.

5.1 )Creating Your Directories

We'll create some directories to base our lab work in..

~/ee295 will contain all your course work
 

~/ee295/lab1

contains your work for this lab




Commands in Red are to be typed at the kshell prompt
Instructions:
1. Log into a workstation and from your home directory..

 
2. mkdir ee295
3. cd ee295
4. tar -vxf ~jswift/public/lab1.tar

x lab1, 0 bytes, 0 tape blocks
x lab1/.synopsys_vss.setup, 157 bytes, 1 tape blocks
x lab1/WORK, 0 bytes, 0 tape blocks
x lab1/vhdl_source, 0 bytes, 0 tape blocks
x lab1/vhdl_source/adder.vhd, 2830 bytes, 6 tape blocks
x lab1/vhdl_source/gates.vhd, 3096 bytes, 7 tape blocks
x lab1/vhdl_source/testadder.vhd, 4186 bytes, 9 tape blocks
x lab1/DLX, 0 bytes, 0 tape blocks
x lab1/run_sim, 13 bytes, 1 tape blocks
 
5. cd lab1

5.2) Preparing Your Execution Evironment

You'll need to set some environment variables before continuing. Since you need to set these variables everytime you run v-system it's usually best to prepare a little script file that contains these steps and run it each time you need to run v-system.

UVM Setup file:

IBM Setup file:

Instructions:

1. check your lab1 directory for file called setupVCS
      #  dot execute this file:    . setupVCS.ksh

Remember: This Script Must be Run Every Time you Log in to Run Labs With V-System.

5.3) VCS synopsys_vcs.setup Customization File

VCS Uses This File to Identify Locations of VHDL Libraries in the File System. VCS Looks for This File in:
• the Current Directory
• or Your Home Directory
• or in the VCS Installation Directory.
Remember: VCS CAN NOT WORK Without This File. Problems with running V-system often stem from not finding the intended .synopsys_vcs.setup file and using one of the default files listed above.

Instructions:

• Check for this file in your ~/ee295/lab1 directory
• Subsequent labs will update this file

5.4 ) Analyzing Sample VHDL

At This Point You Should Be Able to Execute VCS Commands. We'll start with a simple VHDL design.

Instructions:

• cd ~/ee295/lab1
• Enter: 

jswift@chic:/afs/btv.ibm.com/u6/jswift/lab1
$ vhdlan vhdl_source/gates.vhd
Synopsys 1076 VHDL Analyzer Version 2000.12 -- Dec 07, 2000

                Copyright (c) 1990-2000 by Synopsys, Inc.
                            ALL RIGHTS RESERVED
 

jswift@chic:/afs/btv.ibm.com/u6/jswift/lab1
$ vhdlan vhdl_source/adder.vhd
Synopsys 1076 VHDL Analyzer Version 2000.12 -- Dec 07, 2000

                Copyright (c) 1990-2000 by Synopsys, Inc.
                            ALL RIGHTS RESERVED
      
$ vhdlan vhdl_source/testadder.vhd

5.5) Elaboration

We've analyzed enough example designs to run the simulator. We can either run the simulator using a graphic interface or the command line. Scirocco Compiler expands the
design hierarchy given a design root, and produces the executable
binary file for simulation.

Enter:

$  scs test_adder_behavioral
scs -- Scirocco Compiled Simulator

Version Scirocco-2002.12.1 -- Apr 28, 2003
Copyright 1995-2003 by Synopsys Inc., ALL RIGHTS RESERVED

5.6) Execution

We've analyzed enough example designs to run the simulator. We can either run the simulator using a graphic interface or the command line.


Command Line

$ scsim
scsim -- Scirocco Compiled Simulator

Version Scirocco-2002.12.1 -- Apr 28, 2003
Copyright 1995-2003 by Synopsys Inc., ALL RIGHTS RESERVED

This program is proprietary and confidential information of Synopsys Inc.
and may be used and disclosed only as authorized in a license agreement
controlling such use and disclosure.

#                        <<--- command prompt

Execute the model for 1000 nSec
# run 1000
600 NS
Assertion ERROR at 600 NS in design unit TESTBENCH(ADDER8) from process /TESTBENCH/TEST:
    "Sum is 00000111. Expected 00001000"
# 




GUI

After a pause a motif window should appear

2) Push OK Button

3) Open a waveform view. Notice though, there are no signals present.

4) Open a hierarchiy viewer

Select the top signal and group select the rest of the signals and drag+drop them on to the waveform viewer.
Select = left click of mouse button ( or LM )
Group Select = shift + LM

Drag+drop = Shift + middle button ( or LM + RM on a 2 button PC mouse )  

5.7) Questions

There are many features to help you debug your designs in this product that we don't use in this lab. Take some time to get familiar with the product documentation.

By navigating within the waveform viewer, answer the following questions:
1. What is the value of cout at 700ns?
2. What are the values of a & b in HEX at 700ns?
3. What is the sum of a + b + cin at 600ns?
4. How long was the total simulation?




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Copyright 2003, J Swift , UVM
Copying this document without the permission of the author is prohibited and a violation of international copyright laws.