LAB4) Synthesizing the ALU

In this lab we introduce logic synthesis to the methodology, processing our macros from the first labs. We will use Synopsys (TM ) Design Compiler and Chips Express technology library descriptions to create structural netlists of technology-mapped library cells.

Outline

1) References:

• Synthesis Quick Reference
• HDL Compiler for VHDL
• Guide to HDL Coding Styles for Synthesis
• Design Compiler User Guide
• Design Compiler Reference Guide
  

2) How Design Compiler Works

set search_path \                                                                                                     
{. /afs/btv/data/uvm_class/chips_express/lib/synopsys/cx3003 \                                                        
   ~jswift/uvm_class/chips_express/lib/synopsys/cx3003 \                                                              
   synopsys_root + "/libraries/syn" };                                                                                
set link_library  { cx3003_core.typ.db  };                                                                            
set target_library  "cx3003_core.typ.db";                                                                             
set symbol_library  "cx3003_core.typ.sdb";                                                                            
                                                                                                                      
define_design_lib WORK      -path ~/ee295/lab4/WORK                                                                   
define_design_lib IEEE_EXTD -path ~/ee295/lab4/IEEE_EXTD                                                              
                                                                                                                      
analyze -library IEEE_EXTD -format vhdl "~/ee295/lab4/vhdl_src/stdl1164_vector_arithmetic.vhd"                        
analyze -library IEEE_EXTD -format vhdl "~/ee295/lab4/vhdl_src/stdl1164_vector_arithmetic-body.vhd"                   
analyze -library IEEE_EXTD -format vhdl "~/ee295/lab4/vhdl_src/stdl1164_extended.vhd"                                 
analyze -library IEEE_EXTD -format vhdl "~/ee295/lab4/vhdl_src/stdl1164_extended-body.vhd"                            
                                                                                                                      
analyze -library WORK      -format vhdl "~/ee295/lab4/vhdl_src/dlx_types.vhd"                                         
analyze -library WORK      -format vhdl "~/ee295/lab4/vhdl_src/alu.vhd"                                               
elaborate alu -library WORK  -architecture behavior                                                                   
                                                                                                                      
check_design                                                                                                          
set_max_area 2000                                                                                                     
set_load 20 "result"                                                                                                  
set_max_delay 16  -from s1 -to result                                                                                 
compile  -map_effort high                                                                                             
                                                                                                                      
set vhdlout_dont_write_types  true                                                                                    
set vhdlout_write_components  false                                                                                   
set vhdlout_write_entity  false                                                                                       
set vhdlout_use_packages  { ieee.std_logic_1164.all cx3003_core.vcomponents.all work.dlx_types.all work.alu_types.all }
write  -format vhdl -hierarchy  {"alu"} -output ~/ee295/lab4/vhdl_src/alu_gates.vhdl                                  
                                                                                                                      
report_timing                                                                                                         
report_area                                                                                                           
exit                                                                                                                  
 

  3) Preparing to run Design Compiler

Note the timing and area report results

Running Interactive Style with the GUI.
3.6) Enter
$ design_analyzer &
[1]     35188


Use the read pulldown menu

4) Synthesis Experiments