DLX Project

Your labs have involved rewriting portions of the DLX design . For the final project you will compile and run the origional DLX from the author's web page and introduce your RTL and gate level ALU's and re-run the testbench verifying that you haven't 'broken' the origonal DLX design.

1) Compiling the DLX

jswift@eda07:/afs/btv.ibm.com/u6/jswift/my_ee295
$ tar -vxf /afs/btv.ibm.com/u6/jswift/public/project.tar
x project
x project/vhdl_source
x project/vhdl_source/alu-behavior.vhdl, 1766 bytes, 4 media blocks.
x project/vhdl_source/alu.vhdl, 358 bytes, 1 media blocks.
x project/vhdl_source/alu_types.vhdl, 684 bytes, 2 media blocks.
x project/vhdl_source/clock_gen-behavior.vhdl, 512 bytes, 1 media blocks.
...
x project/work
x project/work/_info, 67 bytes, 1 media blocks.
x project/make_dlx, 1775 bytes, 4 media blocks.
x project/modelsim.ini, 10462 bytes, 21 media blocks.
x project/bv
x project/bv/_info, 67 bytes, 1 media blocks.

Change directory to project and prepare for simulation

jswift@eda07:/afs/btv.ibm.com/u6/jswift/my_ee295
$ cd project
jswift@eda07:/afs/btv.ibm.com/u6/jswift/my_ee295/project
$ . setupModelsim
Preparing MTI Environment
Initalization setup complete

This time the libraries are already set up and a make file is provided to compile the various DLX constituents:

various types packages,
alu( behavior and SYN_Behavior ),
bv_arith, controller,
reg_file,
various registers,
instruction register extender,
mux
latch
structural top level of dlx(rtl) in dlx-rtl.vhdl that instantiates the above
configuration dlx_rtl for dlx(rtl) in dlx_rtl.vhdl

and a top level test bench dlx_test(bench) that instantitates

memory, pre-loaded with a small program
clock generator
top level dlx(rtl)
configuration dlx_test_rtl for dlx_test(bench)
NOTE - this is what you will be loading and running

There are several alternative to the configuration I've selected including

memory that fetchs it's contents froman external file
various testbench architectures

2) Copy your gate level alu from lab 3

jswift@eda07:/afs/btv.ibm.com/u6/jswift/my_ee295/project
$ cp ../lab3/alu_gates.vhdl vhdl_source/

Make sure you have only entities for ythe lower level alu_DW* macros, not for the alu itself ( as we discussed in class )
In case you need a reminder, you need to comment out the alu entity declaration from your alu_gates.vhdl file

jswift@eda07:/afs/btv.ibm.com/u6/jswift/my_ee295/project
$ grep entity vhdl_source/alu_gates.vhdl
entity alu_DW01_add_33_0 is
entity alu_DW01_sub_32_1 is
entity alu_DW01_sub_32_0 is
entity alu_DW01_add_32_0 is
--entity alu is

3) Run the make_dlx script

jswift@eda07:/afs/btv.ibm.com/u6/jswift/my_ee295/project

$ . make_dlx | more - or - > console either pipe this into more or redirect into a console file in case you need to check it later
Model Technology ModelSim SE vcom 5.5e Compiler 2001.10 Oct 2 2001
-- Loading package standard
-- Loading package std_logic_1164
-- Loading package numeric_bit
-- Compiling package dlx_types
Model Technology ModelSim SE vcom 5.5e Compiler 2001.10 Oct 2 2001
-- Loading package standard
-- Compiling package alu_types
Model Technology ModelSim SE vcom 5.5e Compiler 2001.10 Oct 2 2001
-- Loading package standard
-- Loading package numeric_bit
-- Compiling architecture behavior of alu
-- Loading package std_logic_1164
-- Loading package dlx_types
-- Loading package alu_types
-- Loading entity alu
Model Technology ModelSim SE vcom 5.5e Compiler 2001.10 Oct 2 2001
-- Loading package standard

4) Run the simulation

You can either invoke vsim as we did for the gate level simulation and avoid the graphical menus

jswift@eda07:/afs/btv.ibm.com/u6/jswift/my_ee295/project
$ vsim -c dlx_test_rtl -do "run -all; exit"
Reading /afs/btv/data/uvm_class/modeltech/rs6000/../tcl/vsim/pref.tcl

# 5.5e

# vsim -do {run -all; exit} -c dlx_test_rtl
# // ModelSim SE VHDL 5.5e Oct 1 2001 AIX 3
# //
# // Copyright (c) Mentor Graphics Corporation, 1982-2001, All Rights Reserved.
# //                       UNPUBLISHED, LICENSED SOFTWARE.
# //            CONFIDENTIAL AND PROPRIETARY INFORMATION WHICH IS THE
# //          PROPERTY OF MENTOR GRAPHICS CORPORATION OR ITS LICENSORS.
# //
# // Copyright (c) Model Technology Incorporated 1990-2001, All Rights Reserved.
# //
# Loading /afs/btv/data/uvm_class/modeltech/rs6000/../std.standard
# Loading /afs/btv/data/uvm_class/modeltech/rs6000/../ieee.std_logic_1164(body)
# Loading ./work.dlx_types
# Loading ./work.dlx_test_rtl
# Loading ./work.dlx_test(bench)
# Loading ./work.clock_gen(behavior)
# Loading ./bv.bv_arithmetic(body)
...
# Loading ./work.mux2(behavior)
# Loading ./work.ir_extender(behavior)
# Loading ./work.controller(behavior)
# run -all; exit
# ** Note: initializing
#    Time: 0 ns Iteration: 0 Instance: /dlx_test/proc/the_controller
# ** Error: illegal function code                                                    <-- note this is expected at time: 0ns
#    Time: 0 ns Iteration: 0 Instance: /dlx_test/proc/the_alu
# ** Note: fetching instruction
#    Time: 70 ns Iteration: 1 Instance: /dlx_test/proc/the_controller
# ** Note: ADDI     R2, R0, 0
#    Time: 188 ns Iteration: 0 Instance: /dlx_test/proc/the_controller
...
# ** Note: decode, source register read and PC increment
#    Time: 8950 ns Iteration: 1 Instance: /dlx_test/proc/the_controller
# ** Note: execute
#    Time: 8968 ns Iteration: 0 Instance: /dlx_test/proc/the_controller
# ** Note: TRAP instruction encountered, execution halted
#    Time: 8968 ns Iteration: 0 Instance: /dlx_test/proc/the_controller
^C# Simulation stop requested

Note - when I run -all this testbench seems to go into an infinite loop after this step and I need to either cntl-c in batch ot kill the process in graphical mode. However, the TRAP instruction is a successful completion of the program. One solution is to use "run 8968;" instead of -all.

Or you can run vsim using the gui ( just enter vsim ) and follow along

5) Run the simulation with alu(SYN_Behavior)

There are several ways to introduce our gate level alu, the easiest change ( avoiding creating more configurations ) is to modify the dlx_rtl configuration's alu entry as follows.
Comment out the original alu(behavior) spoecification and create a nearly idential one for alu(SYN_behavior)

and re-compile the 2 configurations
jswift@eda07:/afs/btv.ibm.com/u6/jswift/my_ee295/project
$ vcom -93 vhdl_source/dlx_rtl.vhdl vhdl_source/dlx_test_rtl.vhdl
and re-run the vsim step #4. NOTE - now the console reflects loading in our gate-level alu's various components.

# Loading ./work.dlx_rtl
# Loading ./work.dlx(rtl)
# Loading ./work.latch(behavior)
# Loading /afs/btv/data/uvm_class/modeltech/rs6000/../std.textio(body)
# Loading /afs/btv/data/uvm_class/modeltech/rs6000/../ieee.vital_timing(body)
# Loading /afs/btv/data/uvm_class/cx3003_core.vcomponents
# Loading ./work.alu(syn_behavior)
# Loading /afs/btv/data/uvm_class/modeltech/rs6000/../ieee.vital_primitives(body)
# Loading /afs/btv/data/uvm_class/cx3003_core.vtables
# Loading /afs/btv/data/uvm_class/cx3003_core.hilo(vital)
# Loading /afs/btv/data/uvm_class/cx3003_core.cx5222(vital)
# Loading /afs/btv/data/uvm_class/cx3003_core.oa4133(vital)
# Loading /afs/btv/data/uvm_class/cx3003_core.iv10d(vital)
# Loading /afs/btv/data/uvm_class/cx3003_core.nd20d(vital)
# Loading /afs/btv/data/uvm_class/cx3003_core.ao4222(vital)
# Loading /afs/btv/data/uvm_class/cx3003_core.ad20(vital)
# Loading /afs/btv/data/uvm_class/cx3003_core.or41(vital)
# Loading /afs/btv/data/uvm_class/cx3003_core.ao4135(vital)
# Loading /afs/btv/data/uvm_class/cx3003_core.ao4221(vital)