EE295 - ASIC Design With VHDL Class - Fall 2002

Composite Types and Operations

Outline:

• Arrays
• Examples of Array Declarations
• Multidimensional
• Array Aggregates
• Array Attributes
• Unconstrained Array Types
• Examples of Unconstrained Vectors: Strings, Bit_Vectors, Std_ULogic_Vector
• Unconstrained Array Ports
• Array Operations
•  Defined
•  Boolean
•  Shift
•  Relational
•  Concatenation
• Array Slices
• Record
• Example

Arrays

• Indexable Set of Identical Objects
• Enumerations are Arrays
• Vectored Signals/Ports are Arrays
• Arrays may be Multi-Dimensional
• May Model Actual Storage Devices ( SRAM, GRAM, DRAM )

---

Examples:

--declares array type
type mem_address is array ( 31 downto 0 ) of bit;
variable A, B : mem_address;
..
A <= B; -- 32 bit assignment
A(1) <= b(31); -- bit slice
..
-- an enumeration
type tap_controller_state is array ( idle, write_instr, write_data,... ) ;
variable T : tap_controller_state;
..
if ( T = idle ) then T:= write_instr;

--
subtype ram_addr is integer range 0 to 63 ;
type ram is array ( ram_addr ) of mem_address ;
 
 

---

Multidimensional

Example:
 
type ram_type is ( 0 to 63, 7 downto 0 ) of std_logic;
signal ram : ram_type;
...

initialize : for i in 0 to 63 loop

for j in 7 downto 0 loop
ram ( i, j ) <= '0' ;
end loop;
end loop;

---

Array Aggregates

Example:
 
type word is ( 0 to 7 ) of std_logic;
..
variable status : word := ( 1, 0, 0, 0, ... -- positional association

variable status : word := ( 0 => 1, 1 => 0, 2 => 0, ... --named association

variable status : word := ( 0 => 1, 1 to 7 => 0 ); -- also named

variable status : word := ( 1, others => 0 ); --positional

-- why is others desirable over the previous forms?

---

 

---

For Ascending Ranges..
• array'LEFT = array'LOW
• array'RIGHT = array'HIGH
For Descending Ranges..
• array'LEFT = array'HIGH
• array'RIGHT = array'LOW
array'RANGE / 'REVERSE_RANGE
• Returns a Type Range Value
• Used to Control Loop Iteration
• Describing Growable Macros ( N-Bit Gates, N-Bit RAM )
• Conversion Functions
• Working with Enumerated Types

Unconstrained Arrays

• Powerful Feature
• Up to Now Array Indices have Been Fixed
• VHDL Allows Array Declarations Without Index Bounds Specification
• Deferred Until Specified in Context
• Example:
type stack is array ( natural range <> ) of word;
--subtype applies constraints
subtype short_stack : stack ( 0 to 512 );

---

Examples of Unconstrained Vectors: Strings, Bit_Vector & Std_Ulogic_Vector

Strings
 

type string is array ( positive range <> ) of character;

Bit Vectors
 

type bit_vector is array ( natural range <> ) of bit ;

Standard Logic Vector
 
type std_ulogic_vector is array ( natural range <> ) of std_ulogic;

Unconstrained Array Ports

• Port Declaration - Width Not Specified
• Width of Busses
• Start/Stop Points of Busses
• Macros can be Defined with 'Growable' Interfaces
• Example:
entity and_n is port ( a : in bit_vector, z : out bit );
..
for i in a'range loop

Array Operations and Referencing

Defined Operators:

Boolean Operators
• and, or, nand, nor, xor, xnor
• Arrays of Equal Length
• Paired Bit-wise From Left to Right

---

Shift Operators

• sll, srl, sla, sra, rol, ror
sll, srl
• Shift Left/Right Logical
• Shift Filling Vacant Positions with '0' / False
sla, sra
• Shift Left/Right Arithmetic
• Shift Filling Vacant Positions with Value from Rightmost/Leftmost Position
rol, ror
• Rotate Left/Right
• Shift Filling Vacant Positions with Value Shifted Out of Register
• Example:
• B"10001010" sll 3 = B"0101000"

---

Relational Operators

<

>

<=

>=

/=

=

---

Concatenation

&

---

Array Slices

• Signal data : std_logic_vector ( 0 to 7 );
• Signal reset : std_logic;
• reset <= data (2);

Record Type

• Records Group a Set of Different Type Objects Together
• Under One Name

---

Example

type student is record
name : string;
Soc Sec Number: string;
tuition : real;
..
end record;