EE295 - ASIC Design With VHDL Class - Fall 1998

Basic Modeling Constructs

Assignment:

Read Ch 5
Exercise 7, 9, 11, 12, 13, 16

In Describing Complex Designs we Divide our Descriptions into 2 Basic Categories: External View and Internal View. We discuss a Few Key Constructs. The External View is Described in the Entity - The Internal View in the Architecture. We discuss the VHDL Design Process.

Concurrent Statements
Signal Declarations

Behavioral Descriptions

Signal Assignment
Signal Attributes

'Delayed
'Stable
'Quiet
'Event
'Active
'Last_Event
'Last_Active
'Last_Value

Delta Delay
Delay Mechanisms
Process Statements
Wait Statements
Concurrent Signal Assignment
Concurrent Assert Statements
Passive Processes

Structural Descriptions

Component Instantiation and Port Maps

Design Processing

Analysis
Design Libraries, Library Clauses and Use Clauses
Design Libraries

Entity Declaration

VHDL's External View of an Object

Entities Must Have a Name. Not Much More.. an Empty Declarative Region.
In it's Most Diminutive Form:

Entity name is
Entity ADDER is
end |entity ADDER| ;

The External View Must Declare All Possible Ways In To and Out Of The Design.
Ports Provide ELectrical Connections

Entity ADDER is

--this design has 2 inputs and 1 output
Port ( A : in bit; B : in; Z : out );
--an alternative to first example
Port ( A, B : in; Z : out );

end |entity ADDER| ;

Generics Provide Information Inside the Model

Entity HALF_ADDER is

--A Value to Refer to in the Model
generic ( delay : time | := 2.5 nS |; );
--
Port ( A : in bit; B : in; Z : out );
--additional declarative region discussed later

end |entity ADDER| ;

Ports form Implicit Signals Visible to the Architecture

Architectures

VHDL's Internal View(s) of an Object

Architectures Require a Name Too..

Architecture name of entity's name is
Architecture GATES of ADDER is
--declarative region
--signal, constant, component...

begin
--..
--..description of design
--..
end;

Some Suggested Names:

structural: signal assignments and component instances
behavioral: signal assignments and process statements
dataflow: signal assignments and expressions
Appropriate
Avoid Reusing Entity Name: Hierarchical Processing and Translation may Pose Naming Conflicts

Concurrent Statements

A Broad Class of Constructs
Author Focuses on Elemental Concurrent Statement
The Process

| label:|process | sensitivity list | is
| L1:|process | ( A, B ) | is
begin
--
--sequential statements
--
end;

Duality in the Constructs of the Language

Concurrent: Models Real ELectrical Circuits - Wires
Sequential: Executes in Order - A Traditional Computer Programming Language
Both: Possess Powerful Mechanisms for Expression

Signal Declarations

Defines an Object for Electrical Interconnect in an Architecture
Signal name : type |:= initial value |;
Signal A_int, B_int : bit |:= '1'|;

Behavioral Descriptions

Signal Assignment

signal name <= |inertial|transport| waveform

Two Basic Delay Models

Inertial
Transport

w/ waveform is a value expression |after time expression ;
Put it All Together and..
Simplest Form of Concurrent Assignment

A <= B; -- value of B gets put onto A's Sensitivity List
| something that evaluates to a value in the target's type.
| target of the assignment

The Declaration of signals A and B have triggered the construction
of data structures - lists of driving values.

 time(nS):  2 3 5       a list of all the possible transactions
         _________      is always maintained
value:  A|0|0|1|1

transaction = change in one of the signals in a signal's sensitivity list
event = transaction that results in a signal's change of value

The 'Works':

--Assignment With Delay
D_out <= A and B after 10 nS;
--
--Conditional Assignment
data_out <= data_in when enable = '1' else 'Z'; -- A tri-state buffer
--
--Selective Assignment
with sel select --Signal 'sel' Determines Which one of

a <= sig1 after 2 nS when 0, --Several Possible Signals Drives a
sig2 after ( 2 * rise_delay ) nS when 1, -- Value Onto Signal 'a'
sig3 after 7 nS when 2;

Signal Attributes

signal'DELAYED[(time)]
signal'STABLE[(time)]
signal'QUIET[(time)]
signal'EVENT
signal'ACTIVE
signal'LAST_EVENT
signal'LAST_ACTIVE
signal'LAST_VALUE

Delta Time

A mechanism to allow concurrent assignments to be evaluated correctly before 'real' or simulation time increments.
As a designer simulating a design you will select a time base for the purposes of displaying signal values. Between 'ticks' of the 'real' clock delta time advances to permit signal evaluation.

A <= B;
B <= D;
C <= A;  -- what's going on here? What Value Does 'C' Get?
D <= '1';

Process

Actually a Concurrent Statement! Appears in the Body of an Architecture.
Delimits a Section of Sequential Code
Optional Sensitivity List Indicates Which Signals 'Wake Up' a Process. Alternatively a wait statement must Suspend Execution
Self-Contained Declarative Region
Important Time Does Not Increment in a Process - Not Even Delta Time!! Signal Assignments Don't 'Take Place' Until The ( all ) Process(es) Suspends and Concurrent Execution Resumes.
example:

architecture behavioral of mux
begin

|label:|process |( sensitivity list )|
m1:process ( select ) -- this process wakes up with events on signal select
begin

if ( select = '1' ) then data_out <= a; else data_out <= b; end if;

end process m1;

end architecture behavioral;

Process Labels are a Good Idea - Simulators Allow Lookup by Label

Concurrent Signal Assignment Problem

Signal Assignments May Appear in a Process
However the Results May be Confusing
Because Time Does Not Increment

Values are Placed on the Driver List
But Never Take Place Until the Process Halts and Time Moves On
But You Legally May have Referred to that Signal in the Process. What did you get? Uninitialized Garbage?

Wait Statements

A Process Must be Sensitive to Signals
or
Contain an Explicit Wait Condition
Wait is a Sequential Statement
|label:| WAIT - Halts Process Execution

wait on signal name;
wait until boolean expression;
wait for time expression;

Structural Descriptions

Design Hierarchy Subsystems ( Represented by Components ) Interconnected with Signals
Subsystems Decompose into Other Subsystems
or
Purely Behavioral Structures eg. Processes and Signals

Component Instances and Port Maps

IEEE-87

-- Component Declaration
-- Appears in Declarative Region
Component comp_name is

Generic ( gen_name : gen_type |:= init_value );
Port ( port_name : mode port_type );

End Component

Signal portcon : Bit;
--Component Usage
--Appears in Architecture Body
Label_1: Component comp_name

--Ports May Be Connected Using Two Schemes: Positional or Named
--Positional:
Port Map ( |portcon|Open|, ... );
--Ports are Connected in Order Declared

Efficient, But Ambiguous
If Ports on Component Declaration are Rearranged ..
So are the Interconnections
As Long as Modes are Consistant No Errors are Detected

--Named:
Port Map ( port_name => |portcon|open|... );
--formal => actual
--ports assigned in any order
or a Mix of the Two Schemes
Port Assignments Start Out Positional and Switch to Named

Component Must be Bound or Configured to Underlying Entity/Architecture
Ports may only Connect to Signals
Ports may be Composite Objects ( Records, Arrays, Unconstrained Arrays )
Assigned as Single Object or Decomposed ( Subelemental Association )

IEEE-93

-- Component Declaration
Component comp_name is

Generic ( gen_name : gen_type |:= init_value );
Port ( port_name : mode port_type );