EE295 - ASIC Design With VHDL Class - Fall 1999

Generics

Assignment: Read Ch 12

Outline:

• Generics
  • Parameterizing Behavior
  • Parameterizing Structure

Generics

• A Mechanism for Passing Information into a Model
• May Specify..
  • Delay Value for Signal Assignment Statements
  • Depth of a RAM, Width of a Bus
  • Methodology Specific Information.. eg. Placement of a Cell
• Example Declaration of Entity w/ Generics
• entity ent_name is
• generic ( cell_name : array (0 to 31) of char; t_delay : time := 1.0 nS; ... );
  --delay has a default value

  port ( ..);

  end ent_name;

• May be Deferred Until Elaboration - Specified
  • Through Component Binding.
  • Through Configuration.
  • Each Instance ( or copy ) of a the Model May Have Unique Generic Values
• Or Optionally Given a Default as in Our Example
• Many Uses in Specifying Critical Information at Instance Time and Controlling Design Implimentations.
• Example Specification of Generic Values
• U1:entity work.ent_name
• generic map ( cell_name => "CHQZ"; t_delay => 3.244 nS);
  port map (... );
  • Generic Associations Share Some Common Rules With Ports
    • Named or Positional Association
    • Keyword Open Indicates No Value Assigned

Parameterizing Behavior

• Behavior is Modified Using Generics in Signal Assignments
  outport = inport After t_delay;

Parameterizing Structure

• Used in Conjunction With Unconstrained Vectors
• Define a Common ( Global ) Constraint Throughout the Model
• Example Declaration of Entity w/ Generics
• entity ent_name is
• generic ( width : positive );

  port ( a, b : in bit_vector ( 0 to width-1);
  q : out bit_vector ( 0 to width-1);

  end ent_name;

Return to Class Home Page

z Copyright 1999, James Swift
Copying this document without the permission of the author is prohibited and a violation of international copyright laws.