EE295 - ASIC Design With VHDL Class - Fall 1999

Guarded Signals and Disconnection, Blocks and Guarded Blocks

Outline:

• Normal Signals
• Disconnection
• Guarded Signals
• bus signals
• register signals
•  Guarded Signal Assignments
• Keyword null
• Composite guarded signals
• 'Driving Attribute
• Guarded Ports & Procedure Arguments
• Blocks
• Guarded Blocks

Normal Signals

• Signals Involve Maintaining a List of Possible Contibuting Values
• When We Assign a Variable or an Expression to a Signal the Value gets Placed on the List
• When We Assign a Signal to a Signal
S1 <= S2;
 
We are Placing S2's Driver List on S1's Driver List
Future Updates to S2 Influence S1 Forever More
 
• Resolved Signals Permit Disconnection of a Contributor to a Signal's Driver List
• std_logic & std_logic_vector are examples of resolved signal types
• register & bus Guarded Signals are an Alternative

Guarded Signals

signal signal_name : type [ register | bus ] [ := expression ] ;
 


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Bus Signals

• Through a resolution function Assume a Default Value When All Drivers are Disconnected
• Models a Bus That is Pulled Up, similar to std_logic but more abstract

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Register Signals

• Retain the Last Value Driven on to Them
• Models a Storage Device Like a Register

Guarded Signal Assignment

signal_name <= ( value_expression [ after time_expression ] | null [ after time_expression )] [, ..] ;

Null Indicates that the signal is Disconnected

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Composite Guarded Signals

A Guarded Signal of Composite Type ( e.g. Array, Record ) Must Resolve All of the Values, Connect or Disconnect.

A Composite of Guarded Signals May Be Disconnected Individually.
 

'Driving Attribute

In 1076-93 'driving  is Provided to Determine if a Signal is Disconnected.
In 1076-87 'driving_value Returned the Value Off the Driver List But Is Illegal For a Disconnected Signal
 

Guarded Ports

• Like Signals, Ports May Be Guarded
• Special Behavior



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Guarded Signal Procedure Parameter Declarations Not Permitted

VHDL-87 Varied on Specifying bus on Procedure Parameter Declarations

Blocks

Complex Architectures Should be SubDivided for Clarity
Signals With Block Scope vs Global Signals

Label : block      [ is ]

[generic, generic_map, port, port_map]
-- declarative region
begin
-- concurrent statements
end block [label] ;

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Guarded Blocks

Required for Concurrent Assignment of guarded signals

Label : block  ( boolen_expression )    [ is ]
Label : block  ( boolen_expression )   -- VHDL-87
 
[generic, generic_map, port, port_map]

-- declarative region
begin
-- concurrent statements
s1 <= guarded s2 ;
t1 <= t2 when guard else t3 ..
end block [label] ;
 

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• Guard is an Implicity Defined Signal of Type Boolean
• Only Visible in the Block
• May not be Assigned or Referenced
• Block Execution:
• When Transaction on Signals Appearing in boolean_expression
• boolean_expression is evaluated and guard signal is updated
• if guard is False
• guarded signals are Disconnected
• unguarded signals Assignments Statements are Disabled
• Guard Can be Explicitly Defined and Described for More Complex Behavior