EE295 - ASIC Design With VHDL Class - Fall 2002

Introduction

Assignment: Read Ch 1

 We discuss the VHDL Hardware Description Language Introducing
a Few Key Constructs. We discuss the VHDL Execution Process.

Outline

• Modeling Digital Systems
• Modeling Domains
• What is VHDL?
• History of VHDL
• Reballoting the Standard: 1076-87 vs -93
• Some Useful VHDL Web Resources
• My Entire Resource List
• What is an ASIC?
• What is a Design Methodology
• VHDL Overview:
• Modeling Domains
• VHDL Modeling Concepts
• Test Benches
• Analysis, Elaboration and Execution
• Lexical Elements
• Comments
• Identifiers
• Numbers
• Characters
• Entity / Architecture
• Package / Library / Use
• Process

Modeling Digital Systems

• Hierarchical, Parallel Development
• Rigorously Defined Specification, Restrictive Rules of Scoping & Visibility
• e.g Connections Between Hierarchical Elements are Explicit
• Signals Dont Mysteriously Change Value
• Modularity / Portability/ Extendability

 

 
 
 
 
 

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• Precisely Define Requirements
• Guarantee Correctness
• Allow Flexibility of Implimentation
• Communicate Function to the Customer
• Test & Verification of the Design Function
• Formal Verification  of the Design's Correctness
Footnote: As Dr Ashenden States In 1996 FV Showed 'Bright Promise'; Today it's Increasingly in Production Use and an Emerging Specialty Sector in the CAD Industry

Modeling Domains

What is VHDL?

• VHDL = VHSIC Hardware Description Language
• VHSIC = Very High Speed Integrated Circuit
• Combines Elements of Programming and Traditional Hardware Design
• Promotes Complex Hierarchical Design with:
• Strict Rules of Scope
• Strict Type Enforcement
• Design Library Integrity
• Very Rich and Expressive:
• Operator/Function Overloading
The + (plus) sign is only meaningful for objects of type integer
or related sub-types in the native language but can be precisely defined
by the designer for *any* types.
• User Defined Types -
• Meaningful Enumerated State Values for FSMs
• Binary Enumerated State Values To Meet Implementation Goals
• Bus Values - Valid Instructions for a uProc, Communications Protocol
• Technology Independence
• Specification Seperate from Implimentation

History of VHDL

• DoD interest in Successful System Integration in an Environment of Independent Contractors using Diverse Design Tools and Methodologies.
• 'Wood's Hole Conference', A Brain Trust, Best Minds of IBM TI, Intergraph, Consultants. Mission: Define A Super HDL. Result: VHDL7.2.
• Thrived in IBM AS/400, Many Other IBM Designs, Delighted DoD
• Stalled in Marketplace/Academia
• Move VHDL into IEEE ( ~= Public_Domain ). Additional Review & Refinements. Result: VHDL 1076-87
• Currently about 8 sub-groups in

Test

BSDL - A Test Specific Subset. Mfg Testers Building In Compilers.

Synthesis

Defining Packages of Synthesizable Operators

Simulation

1164 or MVL9 - Providing Multi-Value Types Representing

ASIC Library

VITAL..

• Investigate These More at the VHDL International Users Foundation(VIUF) Home Page

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Useful VHDL Resources:

• VHDL International Users Foundation(VIUF)  has been replaced by Accellera a combinations of VHDL and Verilog proponent groups.

• comp.lang.vhdl
• VIUF comp.lang.vhdl archive FAQ
Part 1: FAQ General (contacts, etc.)
Part 2: Lists of Books on VHDL
Part 3: Lists of Products & Services (PD+commercial)
Part 4: Glossary (if your browser can handle "netscape frames" try this)
• VHDL International ( VI ) Great Newsletter On-Line
• EDA Industry Working Groups

 The one stop Electronic Design Automation (EDA) Standards resource on the World Wide Web!
• VHDL Syntax in Bachus-Naur Form
• Steve's Vital Tutorial

 

 
 
 
 
 

Additional Resources

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Reballoting the Standard - 1076-87 vs -93

• Mandated by IEEE - At least every 5 Years
• Committee Review
• Successful Introduction of
• LRM Contains Much More Information
• More Consistent Syntax
• Improved File I/O
• Reduction in Verbosity
• Most Commercial Simulation Tools Support Fully
• Synthesis Tools Vary - Traditional Restrictions Still Apply

What is an ASIC?

• ASIC = Application Specific Integrated Circuit
• Implements Custom Function According to Description, not Off-The-Shelf
• Described in an HDL ( VERILOG, VHDL ) In an Abstract Technology -Independent Fashion.
• Verified Using a Simulator Product - Analogous to Software Debugger
• 'Mapped' or Translated Using a Synthesis Product
• Implemented in Either Field Programmable, Standard Cell or Gate Array Logic Families.
• Constructed Out of Logical Function Cells ( AND, OR ) and Re-Usable Macro Building Blocks (ADDERs, REGISTERS )
• Re-Usable Cores Increasingly Dominant Part of the Market
• Higher Function Building Blocks Such as UART's, MPEG, PCI
• Available From Foundries or 3rd Party Contractors
• Reduced Risk. Reduced Verification and Synthesis Effort. Shorter Time to Market.
• Connected to External World Through Standardized Protocols and Electrical Interfaces.
• Hard Cold Facts:
• Designer Pays CAD Vendors ~$50K - $500K for Design Tools
• Designer Pays NRE ( ~$200K-.5M ) and Per Part
• Under Agreed Upon Production Volumes Levels.
• Cost = f( Performance, Size, Package )

HINT: Size = f( Synthesis Performance )

• Competitive Environment. Entrepreneurial.
• Short Time to Market.
• Short Successful Product Life Cycle.
• Typical Uses:
• Glue logic to connect uProc to external devices: disk drives, CD-ROM
• Consumer Electronics: Cellular Phones, Games
• IBM Microelectronics

VHDL Modeling Concepts

Let's begin with a simple 4 Bit Register and Introduce a Few Elementary Constructs

An Entity describes the Interface to a Design Object
 

entity REG_4 is

port ( D0, D1, D2, D3, Clk, Enable : in bit;
          Dout0, Dout1, Dout2, Dout3 : out bit )

end entity REG_4;

Elements of Structure

An Architecture describes how that object Behaves..

architecture structural of REG_4 is

signal gated_clk : bit;

begin

G1: entity work.and2(vital) port map ( Clk, Enable, gated_clk );

U1: entity work.dff(vital) port map ( D0, gated_clk, Dout0 );
U2: entity work.dff(vital) port map ( D1, gated_clk, Dout1 );
U3: entity work.dff(vital) port map ( D2, gated_clk, Dout2 );
U4: entity work.dff(vital) port map ( D3, gated_clk, Dout3 );

end architecture structural ;

 Elements of Behavior

Another Architecture Provides an Alternative View of  how that object Behaves..

architecture behavioral of REG_4 isbegin
process is
variable Dout0Var, Dout1Var, Dout2Var, Dout3Var : bit ;
begin
if ( clk = '1' and Enable = '1' ) then
Dout0Var =: D0 ;
Dout1Var =: D1 ;
Dout2Var =: D2 ;
Dout3Var =: D3 ;
end if;

Dout0 <= Dout0Var after 5 ns;
Dout1 <= Dout1Var after 5 ns;
Dout2 <= Dout2Var;
Dout3 <= Dout3Var after 5 ns;
wait on D0, D1, D2, D3, Clk, Enable;

end process;
end architecture behavioral ;

 Lexical Elements

• Structural
• Traditional Schematic Engineering Design Style
• Blocks Interconnected with Wires or Signals
• Behavioral
• Traditional Computer Programming
• Sequential Execution of Instructions
• Abstract, Not Necessarily Physically Realizable
• Data Flow
• RTL or Register Transfer Level
• Combinational Expressions
• Interspersed with Registers to Define  Timing Boundaries
• Gernally Speaking, Physically Realizable

Modeling Concepts

• Structure ( Chap 5, 13 )
• Entity
• Architecture
• Component
• Behavior ( Chap 3, 7 )
• Process
• Procedures
• Functions
• Sequential Subset of the Language
• Dataflow ( Chap 5 )
• Signals, Signal Assignment, Conditional Assignment
• Expressions, Operators, Overloaded Operators
• Register Inference
• Concurrent Subset of the Language

Test Benches

• Many Simulators Possess Proprietary Control Languages = Learning Curve, Non-Portable
• Many are Adopting TCL ( pronounced 'tickle' )
• A Public Domain Scripting  Language
• Alternative is to Use VHDL
• VHDL Design as a Simulation Driver
• No ports on the Entity
• Instaniates Design of Interest
• Uses Processes & Concurrent Expressions to Provide Input Values
• Optionally Compares Output Values Independently
• Full Use of VHDL's Powerful Features - Algorithmic or File I/O

Analysis, Elaboration and Execution - The VHDL Execution Model

The IEEE Language Reference Manual Goes Beyond Syntax and Precisely
Defines the Execution Model to Guarantee Consistent Results.

Analysis
• Insures Adherence to the Language Specification
• Produces Intermediate File
• Targets Library WORK by Default
Elaboration
• Collapsing Hierarchy
• Insures Consistent 'Usage'
• Specification of Deferred Generics
• Sometimes Conceptually Merged into Analysis/Execution for Simplicity

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Analysis, Elaboration and Execution - The VHDL Execution Model - Cont'd

Execution
• Initialization Phase
• time = 0
• Signals Assume Initial Value
• Processes Wake Up and Execute to First Wait
• Changes to Signal Drivers are Stacked Up
• Simulation Cycle
• Time is Incremented to the Next Pending Transaction on a Signal
• Pending Signal Transactions Performed - Possible Causing an Event
• Processes Sensitive to Those Events Wake Up -> New Pending Transactions
• Repeat Until No More Transctions or time = time'high
• Transaction Limit

Lexical Elements

Comments

Comments Appear After Double Dash -- to EOL

Identifiers

• Consist of Alphanumerics ( A-Z, a-z, 0-9 ) and the Underscore
• Start with an Alpha
• May not Contain Back-to-back Underscores or End with an Underscore
• VHDL is Case Insensitive

 

 
 
 
 
 

DFF = Dff = dff       All Refer to the Same Object

• In VHDL-93
• Extended Identifiers Delimited by \  \
• e.g   \This is a really long signal name, isn't it? \
• Are Case Sensitive

 

 
 
 
 
 

DFF     \dff\  are Distinct Objects

• Utilize all ISO Characters Including Blanks

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Numbers

Integer

2 0 127E6

Real

3.0 0.0 127.6E-8

Base 2 - 16

Binary

2#0111#

Hexadecimal

16#0FD#

Octal

8#466#

Exponents

2#1#E8-- base can be any integer 2 - 16

Long Numbers..

May contain Underscores 2#1111_0010_0000_1111#

Characters and Strings

Characters

Delimited by Single Quote 'A', 'B'

String

Delimited by Double Quotes "This contains a ""double quote"" ."

Bit Strings

Binary

B"1111_1010"

Octal

O"466"

Hexadecimal

X"FA"

NOTE - A Bit String is Distinct from an Integer. A Bit String is Distinct from a Signal Value of Type Bit. A Bit String Representing an 8 bit value may not be directly assigned to a vector signal. What to do? More About This Later.

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Transcending The Hierarchical Design Model..

From Bottom to Top

Process

• Actually a Concurrent Statement! Appears in the Body of an Architecture.
• Delimits a Section of Sequential Code
• Optional Sensitivity List Indicates Which Signals 'Wake Up' a Process. Alternatively a wait statement must Suspend Execution
• Self-Contained Declarative Region
• Important Time Does Not Increment in a Process - Not Even Delta Time!! Signal Assignments Don't 'Take Place' Until The ( all ) Process(es) Suspends and Concurrent Execution Resumes.
• example:

 

 
 
 
 
 

architecture behavioral of mux

begin

m1:process ( select ) -- this process wakes up with events on select
begin
if ( select = '1' ) then data_out <= a; else data_out <= b; end if;
end process m1;
end architecture behavioral;

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Entity - Architecture

• Defines a basic design object
• Has a Unique Name
• Example:
• -- An Interface

entity AND4 is
-- a declarative region
port ( a, b : in bit_vector( 0 to 3 ), z : out bit_vector ( 0 to 3 ); );
generic ( power_level : integer := 0 );
end entity AND4;
• at least one of several internal representations or architectures.

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Component Declaration and Instantiation

• Defines another design object
• IEEE-87

Component comp_name
|Generic ( generic_interface_list );|
|Port ( port_interface_list );|
End Component ;
• IEEE-93

Component comp_name |is|
|Generic ( generic_interface_list );|
|Port ( port_interface_list );|
• End Component |comp_name| ;
• analogous to an electrical 'socket' Between Hierarchical Levels
• Represent Objects ( Entities/Architectures )
• We Instantiate Components at the Top Level and BindThem to Entity/Architectures Later

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Package - Library - Use

Package

• 'Containerizes' Reusable Design Objects. Declarations of:
• Components
• Functions
• Constants
• Signals
• Similar Model to Advanced Programming Languages
• Divided into a header ( ~= .h file ) and body that can be separately analyzed. The Interface Can Be 'Visible' While 'Hiding' The 'Implementation'.
• Traditional Mechanism for:
• ASIC Foundries to Deliver Library Support
• CAD Vendors to Provide Tool Support
• Designers to Provide Re-usable Macros

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Library

• The Design Space is Organized into Libraries

WORK

• Default Target of Analysis.
• Library Work is always Visible
• Temptation to Dump Everything Into Work but Don't

IEEE

Collection of Useful Types, Conversion Functions, etc. Through the Use of IEEE Libraries Designs can be More Portable. CAD Vendors can Optimize Design Tools Around Them.

Design Team, Personal

Design

The Design Team Agrees on Reusable Macros and Types to Facilitate Interconnection of the Design, Enhance Productivity or Carefully Control Implementation of Critical Macros.

• The Target Repository of VHDL Analysis.
• The Library Statement Declares Your Dependence on a Library for the Design Object that Immediately Follows.

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Use

Together with the accompanying library statement specifies the exact design objects, package, library combination using ordinary scoping rules.

• Examples:
• Library IEEE;
• Use IEEE.STD_LOGIC_1164.ALL; --reserved word ALL denotes entire contents
• Entity my_design ... --depends on IEEE's package std_logic_1164
• Library LSI_1100; --ASIC Library
• Use LSI_1100.components.AND4; -- Denotes particular part of package
**NOTE
• VHDL Enforces Library Integrity.
• Any Updates to Libraries You Depend On Require You to Re-Analyze
• The Infamous Time/Date Stamp Mismatch Error Message