EE295 - ASIC Design With VHDL Class - Fall 2002

Scalar Data Types and Operations

Assignment:

• Assignment: Read Ch 2

 VHDL borrows from the structured programming technique of utilizing
data types for both the  sequential and behavioral sides of the language.
The full range of types found in such popular programming
languages as C or Pascal is available as well as some electrically
significant ones. Often novice designers find 'type mismatch' errors
in seemingly intuitive assignment statements or expression evaluations.
On the plus side, the use of data types can be a powerful means of
design expression. Remember..

• VHDL is a strongly 'typed' language
• Understanding and utilizing types is important

Outline:

• Data Objects
• Constant
• Variable
• Scalar Types
• Type Declarations
• The Predefined Package Standard
• Discrete Types:
• Integer
• Floating Point ( Real )
• Physical Types
• Enumerated Types
• Bit
• Boolean
• Character
• Severity Level
• Standard Logic ( ieee.std_logic_1164 )
• Type Classification
• Sub Types
• Type Qualification
• Type Conversion
• Attributes
• Expressions

Data Objects..

• Signal - Electrical Interconnection of all Objects
• Appears in any Legal Declarative Region
Signal sig1 [, sig2, sig3...] : signal_type := initial_value;
 

--signl assignment
sig1 <= '1' ;
 

• Variable - Storage of Temporary, Local Information Variable ..
• Constant - Convenient representation of permanent information constant ..

Constants

• Useful Technique in Making Designs..
• Readable
• Re-Usable
• Maintainable
• Design Product Life Time Issues
• Recycling ( Even Designs! ) is Big Business = Cores
• Use Constants, Comments, Data Types to Make Your Design Clear!!!
• Syntax:
constant identifier {,...} : type := expression ;

• Example declaration:
constant pi : real := 3.14 ;
constant width : integer := 32 ;

Variables

• Used to Store ( or remember ) Temporal Information

 intermediate calculations

• Variable Assignment Inherently More Efficient Than Signal Evaluation
• Signals Require a Driver List
• Signals Must Allow for Attributes - Additional Overhead
• Variables Take Less Memory Overhead
• example declaration:
--appearing in any sequential declarative region
variable identifier {,...} : type [:= initial value expression ] ;
variable total : integer := 0 ;
• example assignment:
--appearing in body of a process, procedure or function
total := total + 1 ;

Type Declarations

• Extends the Native set of Predefined Types
• Declares a type name and legal values
• Types declared seperately, even with the same values,  are distinct, incompatable types.
• Example:
type type_name is type_definition ;
type date is range 1 to 31 ;
type my_rev_int is range 27 downto 5 ;
• type day is ( sunday, monday, tuesday, .. ) ;

The Predefined Package Standard

• Refer to Appendix B
• There is a Package called Standard in Library std
• Defines Predefined or Built-in Types, Sub-types, and Functions of VHDL
• It is Always Visible

Integer

• Default Range -2,147,483,647 to 2,147,483,647 ; -- 32 bit signed
• We May Define Integer Types That are Range Constrained

 

 
 
 
 
 

 Type day_of_month is range 0 to 31 ;

note This is a unique type, it is not the same as Integer.

---

Integer Operators

• operators:

+

addition, identity

-

subtraction, negation

*

multiplication

/

division

mod

modulo

rem

remainder, A rem B is the remainder left over after A is divided by B

abs

absolute value

**

exponentiation

Floating Point ( Real )

• Range -1.0E+38 to +1.0E+38 -- 6 decimal place accuracy
• Constrained to a range
type temp is range -40.0 to 100.0;
• Operators:
 
+
addition, identity
-
subtraction, negation
*
multiplication
/
division
abs
absolute value
**
exponentiation

Physical Types

• Represent real-world physical quantities
e.g length, mass, time, current
• Syntax:

 

 

type <type_name> is range simple_expression (  to |  downto ) simple_expression

units
identifier ;  -- primary unit
{identifier = physical_literal ; }  --secondary units
end units [ type_name ] ;
 
• Primary unit defines the smallest resolution that can be represented
• Secondary units must be an integer multiple of Primary units
• Example: Predefined Type Time
type time is range 0 to MAX_INT ;
 
units
fS;
pS = 1000 fS; --picosecs
uS = 1000 pS; --micro
nS = 1000 uS; --nano
mS = 1000 nS; --milli
sec = 1000 mS;
min = 60 sec;
hr = 60 min;
end units;
• Often used to represent delay in signal assignments
• fS is the resolution limit
• Time values smaller are rounded down to 0
• Simulators allow us to specify a larger resolution limit
• Events are only represented at this limit
• Reduces simulation overhead
• Allows model to simulate for a longer period of time
• Any Kind of Physical Type can be Defined

Current

na, ua, ma, a

Voltage

mv, v, ..

Temperature

Enumerated Types

• Enumerated Objects Take on One of a Possible List of Values
• Boolean : ( true, false )
• Logical Operators: and, or, nand, nor, xor, xnor, not
• Character : ( 'A', 'B', 'C', .. )
• Basic Signal Types are Enumerations
• Some Examples:
• Bit : ( 0, 1); --Builtin
• Logical Operators: and, or, nand, nor, xor, xnor, not
• But bit and boolean are not identically matched types.
• Useful in Design of Finite State Machines to Express Meaningful State Values
e.g Reset, Idle, Awaiting_Request_Acknoledge
• Initial Value Defaults to left-most Element

Character

type character is ( nul, esc, ..., ' ', 'A', '0',
-- Enumerated Mix of Identifiers and Chraacter Literals

VHDL-87
Consists of First 128  ISO Chracters

VHDL-93
Consists of all 256 ISO  Chracters

Boolean

type boolean is ( false, true );

Relational Operators    =,  /=, <, <=, >, >=

Any Ordered Arguments Return Boolean
Logical Operators and, or, nand, nor, xor, xnor, not
Boolean Arguments Return Boolean
Short Circuit Operators - Only Evaluate Right Argument If Left Arg Does Not Determine Result
VHDL-87
xnor is not a defined logical operator

---

Bit

type boolean is ( '0', '1' );

IEEE Standard Logic

type Std_Logic is ( 'U', 'X', '0', '1', 'Z', 'W', 'L', 'H', '-' );

Incorporates Driving ( or Strength ) Values
 

Std Logic Values and What They Represent

U	Uninitialized
X	Forcing Unknown
0	Forcing Zero
1	Forcing One
Z	High Impedance
W	Weak Unknown
L	Weak Zero
H	Weak One
-	Don't Care

Type Classification:

Sub Types

• Constrains a Base Type
• Eases Use of Selected Signal Assignments and Case Statements
• Remember: You Need to Account for All Possible Values
• More Expressive: Natural vs Integer
• Sub Types are Assignment Compatible with Their Base Type
• Example:
Type Integer IS -2,147,483,647 to +2,147,483,647;
Subtype Natural is Integer range 0 to +2,147,483,647;

Type Qualification

• A value may be Ambiguous in Certain Contexts
• e.g.. A string literal is defined in more then one context
• Often the Case with Sub Types
• example:
• --if we have 2 types declared
• type t1 is ( reset, next, ..
• type t2 is ( reset, s1, s2 ..
• ..
• --then .. t1'reset .. --disambiguates the context

Type Conversion Functions

 We discussed the strongly enforced Typing
that's part of VHDL. Conversion Functions are your means of satisfying
these type matching requirements.

• Simplest Form - Between Native Types
• single_signal <= bit ( data_bus( 0 ) );
• --Note resemblance to function call syntax
• Between Declared Types, Vendor Provided Types..
• Vendors Often Provide These in a Package
• Underlying Assumption: Types have a Straightforward Relationship
• i.e.. Natural to Bit
• Would you try Real to Integer?

---

Typical Structure:

FUNCTION t1_to_t2 ( a : t1 ) RETURN t2 IS
BEGIN
CASE a IS
WHEN t1_val => RETURN t2_val
...
repeat as necessary
END CASE;
END t1_to_t2;

---

VHDL-93 In a Component Port Map

ARCHITECTURE portfunc IS
TYPE my_type
COMPONENT AND PORT ( A1 : bit;..
SIGNAL my_sig : my_type;
FUNCTION my_to_bit ( s : my_type ) RETURN bit IS
BEGIN
U1:AND PORT MAP ( A1 => my_to_bit( my_sig ), ...
END portfunc;

Attributes of Scalar Types

T'high

Returns Upper Bound of a Type/SubType

T'low

Returns Lower Bound of a Type/SubType

T'left

Returns Left-Most ( or First ) of a Type/SubType

T'right

Returns Right-Most ( or Last ) of a Type/SubType

T'ascending

Returns true if Type is Ascending, false otherwise

 

 

VHDL-93 Only

T'image(x)

Returns a string representing the value of x

T'value(s)

Returns the value in Type that is represented by s

---

Attributes of Scalar Types - Discrete & Physical Types

type'pos(x)

Returns Position of x in T

type'val

Returns Lower Bound of a Type/SubType

type'succ

Returns Left-Most ( or First ) of a Type/SubType

type'pred

Returns Right-Most ( or Last ) of a Type/SubType

type'leftof

Returns true if Type is Ascending, false otherwise

type'rightof

Returns true if Type is Ascending, false otherwise

 

 

---

Expressions

In Order of Precedence - Highest to Lowest

miscellaneous

abs - Absolute Value of Any Numeric

not - Inversion of Type Bit

** - Exponentiation of Integer or Floating Point to an Integer Power

---

multiplication

*

/

mod

rem

Integer and Floating Point

* and / Are Defined For Physical and Integer, Physical and Real, Physical and Physical

---

sign

+

-

adding

+

-

• For any Numeric Type

& - concatenation

• For One-Dimensional Arrays

---

 

shift - VHDL-93

sll - shift left logical

srl - shift right logical

sla - shift left arithmetic

sra - shift right arithmetic

rol - rotate left

ror - rotate right

---

 

relational

= - equals

/= - not equals

< - less than

<= - less than or equals

> - greater than

>= - greater than or equals

Must Compare Objects of Same Type

Returns Type Boolean

---

 

logical

and

or

xor

xnor VHDL-93

nand

nor

Returns type Bit ( '0' or '1' ) or Boolean ( True or False )

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© Copyright 1999, 2002 James Swift
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