EE295 - ASIC Design With VHDL Class - Fall 2002

Sequential Statements

Assignment:

• Read Ch 3

 We discuss Sequential Processing, the use of contemporary
programming practices to effectively model system behavior. The
System is, of course, not limited to CMOS ASIC Chips. Fiber Optic
Channels, Satellite Uplinks, LANs.. These are the building blocks
of some of today's systems. In this environment accurate electrical
modeling is compromised from powerful forms of expression: Complex
Data Structures and Algorithmic Processing.

VHDL includes a structured programming language and a clean,
well disciplined interface between the concurrent environment and
the sequential environment.

Outline

• What is Sequential Processing
• Signal Evaluation vs Variable Assignment
• Signal Assignment Within a Process
• The Process Statement
• The Assert Statement
• Sequential Statements:
• If
• Case
• Null
• Loop
• Next/Exit
• Wait
• Return

---

What is Sequential Processing?

• Appear in Processes and Sub-Programs
• Statements are Executed in Order
• Variables are Assigned Values
• Mathematical Operators
• Time Does Not Increment! Not Even Delta Time!
• Must Indicate What Signals Activate the Process

---

Signal Evaluation vs Variable Assignment

• Signals model real electronic circuit behavior more accurately

 but

• To Do So Carries More Processing Overhead for Simulation
• Variables are More Efficient Models of Abstract Behavior

 but

• Compromise Real Circuit Modeling

---

Concurrent Signal Assignment Problem

• Signal Assignments May Appear in a Process
• However the Results May be Confusing
• Because Time Does Not Increment
• Values are Placed on the Driver List
• But Don't Take Place Until the Process Halts and Time Moves On
• But You Legally May have Referred to that Signal in the Process. What did you get? Uninitialized Garbage?

---

Process

• Actually a Concurrent Statement! Appears in the Body of an Architecture.
• Delimits a Section of Sequential Code
• Optional Sensitivity List Indicates Which Signals 'Wake Up' a Process. Alternatively a wait statement must Suspend Execution
• Self-Contained Declarative Region
• Important Time Does Not Increment in a Process - Not Even Delta Time!! Signal Assignments Don't 'Take Place' Until The ( all ) Process(es) Suspends and Concurrent Execution Resumes.



---

example:

architecture behavioral of mux

begin
 

m1:process ( select ) -- this process wakes up with events on select
begin
if ( select = '1' ) then data_out <= a; else data_out <= b; end if;
end process m1;
end architecture behavioral;

---

Assert Statement

• Means of Communicating Important Information about the Status of a Design in the Simulation Environment
• Usually Ignored by Synthesis Tools - But May Indicate Potential Hardware Failure.
• Syntax:
Assert condition [Report string] [Severitylevel]
 
• condition Must Evaluate to a Boolean Condition
• When it is False the Statement Executes
• Report string
• string is the Message to be Passed to the Designer's Console
• "Signal has Multiple Drivers With Different Values"
• "Data  Arrived Late"
• Defaults to "Assertion violation."
• Severity level - One of:
• Note
• Warning
• Error
• Failure - Simulation Ceases Execution
• Example:

process ( clock ) is
variable data_var : bit ;
variable pulse_start : time ;
begin
case clock is
when '1' =>
pulse_start := now ;
data_var  := data_in ;
d_out <= data_var ;
when '0' =>
assert now = 0 nS or ( now - pulse_start ) >= 5 nS report "clock pulse too short";
end case;

---

Sequential Statements

• IF
• Conditionally Execute Statements
• Syntax:

      if condition then
           sequential statements...
         [elsif condition then
           sequential statements...]
         [else
           sequential statements...]
         end if;

• Example: Asynchronously Reset Flip-Flop

if enable = '1' then

data_out := data_in ;

end if;

if ( reset = '1' ) then  -- test the reset condition first

Q <= '0' ;

elsif ( clk = '1' and not(clk'stable )) then -- then test for synchronous operation

Q <= Din ;

else

null ;

end if ;

---

• CASE
• Conditionally Select One-of-Many Statements to Execute
• Based on value of selector expression
• There can only be one, unique match. Several choices may be lumped together
• e.g. when choice1|choice2|choice3 => action to perform for all 3 alternate choices
• when add to subtract => action to prefrom for a range of choices
• Syntax:

Case expression is
            when choice => statements..
                ...
            [others statements..;]
            end case;
• Example:

Assuming a type is defined

type alu_func is (pass1, pass2, add, subtract ) ;

Then..

Case func is

when pass1 => result := operand1 ;

when pass2 => result := operand2 ;

when add   => result := operand1 + operand2 ;

when subtract => result := operand1 - operand2 ;

end case;

• choice Indicates a Value the Expression May Take On
• All Possible Choices Must be 'Covered'
• Use of others Simplifies This
• null; -- do nothing quickly
• Often When Applying 'Others' The Desire is to 'Do' Nothing - Hence the Null;
• So Can Use of a Sub-Type to Constrain the Choices

---

• LOOP
• Executes a group of statements repeatedly

[label:] iteration scheme loop condition

{sequential statements}

end loop [loop_label];

• Where iteration scheme may be:
while condition

for identifier in range
 

• Identifier is Self-defining
• Visible Only in the Loop
• Range Specifications:
• i in 0 to 7
• letter in ( 'A', 'B', 'C')
• j in 7 downto 0
• Examples:

Infinite loop..
loop
wait until clk = '1' ;
count := count + 1;
end loop;

Conditional loop..
while  count > 16  loop

wait until clk = '1' ;
count := count + 1;
end loop;

Discrete range loop..
for count in 0 to 15 loop

wait until clk = '1' ;
data_out := data_in(count) ;
end loop;

---

Altering Loop Execution

• And the Following Statements May Alter the Loop Flow:
next - Skip Execution of Following Statements and Iterate Loop

exit - Terminate Execution of the Loop

---

WAIT

- Halts Process Execution
 
wait on signal name;

wait until boolean expression;

wait for time expression;
 

---

• RETURN [expr]
• Indicate the Value a Function Returns.