EE295 - ASIC Design With VHDL Class - Fall 1998
Sub Programs & Packages
Assignment:
Sub-Programs are Important Features of the Language to Describe Design
Hierarchically. Sub-Programs are Procedures and Functions
Packages Provide a Means to Group Re-Usable Design Objects Into a Library
Unit
Outline:
Functions & Procedures
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Contain Re-Usable Design Descriptions
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Body is Sequential - Full Use of Sequential Language Elements
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From the External View Functions ( and Procedures ) are:
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Sequential Statement When Inside a Process ( or Other Sub-Program )
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Concurrent Statement When Outside a Process
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When Declared in Package - Reusable
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When Declared in an Architecture or Process - Local
Procedures
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Generalized Form of Statement
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May Take in and Return Multiple Arguments
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May Not Need Any Arguments
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Example:
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Procedure proc_name ( parm1, parm2 : mode parm_type; parm3.. ) Is
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-- a declarative region
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Begin
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... Sequential Statements
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End |Procedure| |proc_name|;
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--Procedure Use
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A <= B AND C;
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proc_name ( A, B... );
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Unlike Processes, Procedure Variables do not Persist.
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Each Call to a Procedure Creates Newly Initialized Variables
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IEEE-93
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Procedures may be Labelled
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Procedures may use the Result Keyword
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Terminates Procedure and Returns Control to Caller
Procedure Parameters
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Must Have a Mode Declared
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Parameters may be IN, OUT & INOUT
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Procedure proc_name ( parm1, parm2 : mode parm_type; parm3.. ) Is
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Parameters may be Constant|Variable|Signal
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Mode may be In|Out|InOut
Signal Parameters
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Signal is Passed as a Signal Object
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References to the formal parameter are replaced with Signal's Driver List
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Procedure Performs Implicit Wait Statement
Default Values
Parameters are Optional - May Take on Initial Values
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Procedure proc_name ( parm1 : mode parm_type |:= initial_value|
) Is
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Parameters at the End of the Interface List May be Skipped
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-or-
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Keyword Open is Used
Unconstrained Arrays
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Width of Array Parameters may be Deferred
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Procedure proc_name ( parm1 : in bit_vector ) Is
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Inherits Width of Actual Parameter From Caller
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Attributes Essential for Proper Operation
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eg.
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For index In parm1'range Loop
Functions
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Generalized Form of an Expression
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All Parameters are Mode In
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Signals Passed Into Functions as Arguments Carry Attributes
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Returns Only One Argument of the Declared Type
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Used Usually as Part of a Signal Assignment or Expression Evaluation
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parity_bit <= parity ( data_bus );
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--an event on data_bus triggers an assignment to parity_bit
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Declaring a Function:
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IEEE-87
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Function func_name ( arg1, arg2 : mode arg_type; .. ) Return
return_type Is
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-- a declarative region
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Begin
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.. calculates a return value
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Return (value);
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End func_name;
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IEEE-93
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[Pure|Impure] Function func_name ( arg1, arg2 : Mode arg_type; ..
) Return return_type Is
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-- a declarative region
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Begin
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.. calculates a return value
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|Label:|Return (value);
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End |Function| |func_name|;
Pure vs Impure Functions
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In IEEE-87 All Functions Were Pure
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Only Objects Passed Through Interface List Were Visible Inside a Function
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Functions Called With Same Values Always Returned Same Values
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In IEEE-93 It's the Default
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Impure Functions May Refence Signals and Variables Form the Parent
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Result can be Influenced by External Objects
Function Now
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Impure Function Now Return delay_length;
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Returns Actual Simulation Time When Called
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Example in Fig 7-19; pg 214
Overloading
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Overloading Permits
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Similar Functions
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Operating on Different Types
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Have the Same Name
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Declare Functions With Same Name
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Different Number of Arguments
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Arguments of Different Type
Overloading Operator Symbols
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Operators Such as "+", "-", And, Or
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May be Defined to Operate on Extended Set of Objects, User Defined Types
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Function "+" ( L, R : In bit_vector ) Return bit_vector;
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"+" May Now be Used Like the Built-In Infix Operator Defined for Integer
Conversion Functions
In the last class we discussed the strongly enforced Typing
that's part of VHDL. Conversion Functions are your means of satisfying
these type matching requirements.
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Very Popular
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Vendors Often Provide These in a Package
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Underlying Assumption: Types have a Straightforward Relationship
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ie. Natural to Bit
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Would you try Real to Integer?
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Typical Structure:
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FUNCTION t1_to_t2 ( a : t1 ) RETURN t2 IS
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BEGIN
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CASE a IS
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WHEN t1_val => RETURN t2_val
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...
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repeat as necessary
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END CASE;
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END t1_to_t2;
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In a Component Port Map
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ARCHITECTURE portfunc IS
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TYPE my_type
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COMPONENT AND PORT ( A1 : bit;..
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SIGNAL my_sig : my_type;
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FUNCTION my_to_bit ( s : my_type ) RETURN bit IS
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BEGIN
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U1:AND PORT MAP ( A1 => my_to_bit( my_sig ), ...
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END portfunc;
Packages
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Encapsulates Objects that can be Shared or Re-Used
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Forms a Design Unit
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IEEE Defines Some
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Technology Providers and CAD Vendors Can To
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May Optionally be Organized into 2 Parts:
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Header
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Body
Header
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Declaration Section
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Provides a Visible Interface
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IEEE-87
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Package pack_name Is
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--Declarative Region
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Type | Function | Subtype | Constant | Signal(*)
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End pack_name;
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IEEE-93
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Package pack_name Is
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--Declarative Region
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Type | Function | Subtype | Constant | Signal(*)
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End |Package| pack_name;
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Packages May be Accessed With a Library/Use Clause
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Suppose We Have Created a Library my_lib
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Into Which we Have Analyzed Package pack_name
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We Access the Contents of pack_name by..
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Library my_lib;
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Use my_lib.pack_name
SubPrograms in Package Declarations
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Declare Only Header for Procedure or Function
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Name / Arguments & Types / Return Type
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Procedure proc_name ( parm : In parm_type ) ;
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Function func_name ( parm : In parm_type ) Return
func_type ;
Constants in Package Declarations
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Declare Only Constant Name and Type
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Constant const_name : const_type | := const_value |;
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Deferred Constant Values are not Locally Static
Package Body ( Optional )
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Invisible Specification
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Enables Deferred Specification
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Hides Intellectual Property
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IEEE-87
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Package Body pack_name Is
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--Implimentation of Header Objects
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--Additional SubProgram, Type, Constant, File, Alias, Use Declarations
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End pack_name;
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IEEE-93
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Package Body pack_name Is
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--Implimentation of Header Objects
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--Additional SubProgram, Type, Constant, File, Alias, Use Declarations
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End | Package Body | pack_name;
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