Test

Read Ch 14

• Basis of ASIC Test
• Importance of Test
• Boundary Scan Test
• JTAG or IEEE 1149.1
• Scan Test
• Built-in Self Test ( BIST )

Basics of Test

• ASICs are tested in - at least - 2 Stages in Manufacturing

 
• Wafer test - as complete wafers prior to being dicing into individual chips
• Using an array of probes on a probe card
•  Production tester applies signals under control of a test program
• Usually functional patterns at product speed ( ~ Mhz )
• Test program developed by customer, ASIC manufacturer or both

 
• Final test - individual chips packaged into finished product
• Same test patterns applied to 1 ASIC at a time
• In addition the customer will consider testing
• Incoming test - verifies quality of incoming products
• Printed Circuit Board ( PCB ) test - ASIC products mounted on sub-assembly
• Usually 10X more expensive to repair - replace defective ASIC
• System test - all components of the finished product assembled
• Usually 100X more expensive to replace defective ASIC

 
• Defective ASICs may be returned to the manufacturer for failure analysis
• Retest the product
• Possibly refine the test program
• Physical analysis
• Grind away layers and attempt to locate physical defect
• Provide manufacturer with information on the process

 
• Possible defect mechanisms
• Inadaquate testing
• Electro-static discharge
• Improper manufacturing/handling at teh customer site

 

 
 
 
 
 

• FPGA's
• Tested as a programable device - programmed by the customer

 
 

The Importance of Test

One measure of product quality is the defect level

• Company sells 100,000 chips and 10 are defective
• defect level is ( 10 / 100K ) =  0.01 % or 100 ppm ( parts per million )
• AQL ( or average quality level ) is ( 1 - defect level ) or 99.99 %

 
• Assume: Customer buys 100,000 of the chips at $10 / pc
• $200 / PCB to repair

 

ASIC defect level	Defective ASICs	Total PCB repair cost ($)
5%	5000	1M
1%	1000	200 000
0.1%	100	20 000
0.01%	10	2 000

• Assume: System ships 100 000 units @ $5000 ( a $500M program w 10% profit of $ 50 M)
• $10 000  / system to replace in the field
• System defect level of 10%

 

ASIC defect level	Defective ASICs	Defective systems	Total  system repair cost ($)
5%	5000	500	5 M
1%	1000	100	1 M
0.1%	100	10	100 000
0.01%	10	1	10 000

Boundary Scan Test

Traditional Board-level testing had evolved to bed-of-nails fixtures

• that were limited in ability to handle dense surface mount with dual sided components
• Joint Test Action Group ( or JTAG ) proposed on-board circuitry for test purposes
• Became IEEE 1149.1
• Consists of a package interconnect test, at a minimum
• Extendable, may include other tests
• 

JTAG

• 4 wire interface call the TAP or Test Access Port
• TCK - Test Clock
• TDI - Data in ( seriel )
• TDO - Data out
• TMS - Mode Select
• TRST* or nTRST - Optional  Reset
• Building Blocks
• BR  - Bypass Register
• BSC - Boundary Scan Cell
• TDR - Test Data Register, a group consisting of the following
• BSR -  Boundary Scan Register, A shift register of BSCs
• IDCODE - Optional TDR with MFG identification code
• IR - Instruction Register
• TAP -  Test Access Port controller, a state machine to control the flow of data through the registers

 

Boundary Scan Structure

TAP Controller States

BSDL ( Boundary Scan Description Language )

• Extension of the 1149.1 standard

 
• Uses subset of VHDL to describe Boundary sctructures
• e.g Custom test instructuions

 
• Attributes
• identify design ports used for test purposes
• # of instructions
• FSM encoding for instructions
• IDCODE

 

 

Scan Test

• Observability and Controllability
We need the means to detect stuck faults in the ASIC

• Apply Boundary Scan on ASIC internal logic
• Convert DFF sequential elements into scan-able devices

BIST

The next generation of on-board test circuitry is BIST ( or Built-In Self-Test )

• Generates test vectors, applies them and checks the response
• Consists of 2 LFSRs ( or Linear Feedback Shift Register )
• Generates/Predicts Pseudorandom binary sequences

LFSR

BIST Example

MISR ( or Multiple-Input Signiture Register )

Extends the LFSR2 design to accomodate multiple sources
 

DFT ( Design for Test )

• Industry trend is to provide tools to add test structures to a netlist
  e.g Synopsys Test compiler
• May upset critical timing paths, area budgets
• allows design to be portable wrt manufacturing test strategies
• Starts with core design and provides I/O and boundary macros as a top level design that instantiates the core design
• Provides analysis of test coverage using fault simulation and guidance on where / how to add observability
• Produces test vectors