EE295 - ASIC Design Using VHDL

VHDL Synthesis

• Synthesis products translate abstract VHDL statements into circuits and wires using a policy of inference.
• Since some VHDL statements are not 'physically realizable' synthesis tools do not support there use.
• We discuss how abstract VHDL statements infer common CMOS ASIC Library elements. We look at some statements that are difficult to synthesize.

Assignment: Read Ch

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Outline:

• Boolean Expressions
• Control Logic
• Concurrent - Selected Signal Assignment
• Sequential - Conditional Execution
• Components - Entities - Hierarchy
• Functions and Operators
• Storage Elements ( FF's, Latchs, Registers )
• Simple Edge-Triggered Flip-Flop
• Master-Slave Flip-Flop
• Level Sensitive Latch
• Incomplete Specification Problem
• Asynchronous Set/Reset
• Synchronous Set/Reset
• Finite State Machines
• New IEEE 1076.3 ( Synthesis ) Package

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Boolean Expressions

• Any boolean expression is first mapped into a technology independent netlist
• and then a technology dependent netlist.
• Several Equivilant Representations Will beEvaluated
• Demogan's Theorem
• Each Represention is a Unique Solution of Area, Delay ..
• Longest Delay Path Between Registers Determines Overall System Performance
• Distributed vs Consolidated Functions

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Control Logic

We Commonly Encounter 1 Signal Controlling Large, Complex Structures
 Arrays, Records
ILet's look at some simple examples..

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Concurrent - Selected Signal Assignment

 
Data_out <= Q when ( enable = '1'),   -- gated tri-state buffer
'Z' when others ;
 
with data_sel select                        -- 4 way mux
Data_out <= D1 when '00'
D2 when '01'.., ;

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Sequential - Conditional Execution

if ( enable = '1' ) then   -- AND gate, gated tristate buffer, depends..
q <= data_in;
elsif
q <= 'Z';
end if;
 

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Components - Entities - Hierarchy

Lets Review the syntax

Component comp_name is                        -- Declares a Component Object
Generic ( generic_interface_list );
Port ( port_interface_list );
End Component comp_name ;

Label1: Component comp_name                  -- Creates a component instance
Generic map ( generic_association_list )
Port map ( port_association_list ) ;
 
Or in VHDL-93..
Label1: entity ent_name( arch_name )                  -- Creates an entity instance
Generic map ( generic_association_list )
Port map ( port_association_list ) ;
 

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• Means of Instantiating Hierarchical Design Elements
• Instantiating ASIC Library Cells ( I/O Drivers and Receivers ) and Macros ( RAMs, ROMs, Cores )
• If comp_name = Library Cell Name and Port Names Match
• May be Synthesizable and Reconfigurable
• or
• Macros may be Non-synthesizable Behavioural Representation
• Foundry will Insert Physical Representation

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Functions and Operators

Subprograms Are Quite Different Than Components But From A Synthesis Policy Perspective May Also Represent Library Cells.

• Alternate Representation of Macros and Cores
• May Map ( or Represent ) Unique ASIC Macros
• or
• Synthesize out of ASIC Primitives using Instance-Specific Constraints

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Storage Elements

ASIC Storage Library Elements
Registers, Latchs, Scan Latchs
Flip-Flops, JK, MS, SR
 
All Involve  Signal That Retains a Value Over Some Amount of Time

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Simple Edge-Triggered Flip-Flop

Architecture behavioral of dff is
begin
process ( clock )
begin
 
if ( clock = '1' and clock'event ) then
q <= data_in;
end if;
 
end process;
end behavioural;

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Master-Slave Flip-Flop

Architecture behavioral of dff is
begin
Master: process ( p1_clock )
begin
if ( p1_clock = '1' and p1_clock'event ) then
int_q <= data_in;
end if;
end process;
Slave : process ( p2_clock )
begin
if ( p2_clock = '1' and p2_clock'event ) then
q <= int_q;
end if;
end process;
end behavioural;

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Level Sensitive Latch

Architecture behavioral of dff is
begin
 process ( p1_clock, p2_clock, scan_clock )
begin
Scan : if ( p1_clock = '1'  ) then
int_q := scan_in;
end if;
Master : if ( p1_clock = '1'  ) then
int_q := data_in;
end if;
Slave : if ( p1_clock = '1'  ) then
q <= int_q;
end if;
end process;

end behavioural;

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Incomplete Specification Problem

if ( enable = '1' ) then
q <= data_in;
-- elsif
-- q <= 'Z';
end if;
We've Seen This Construct Infer Control Logic and a Latch

Which Is It? We Sometimes Hope For One and Get The Other.

First Notice Most Statements That Have More Than One Outcome Must Specify What Happens For All Possible Outcomes Through The others Keyword.
But Not the if Statement.

By Incompletely Specifying What Happens For Other Values of enable We are
Specifying That Q Holds It's Value and That Infers a Latch Where None was Intended.

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Asynchronous Set/Reset

Architecture behavioral of dff is
begin
process ( set, clock )
begin
 
if ( set = '1' ) then q <= '1';
elsif ( clock = '1' and clock'event ) then
q <= data_in;
end if;
 

end process;
end behavioural;

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Synchronous Set/Reset

Architecture behavioral of dff is
begin
process ( clock )
begin
 
if ( clock = '1' and clock'event )
if ( set = '1' ) then q <= '1';
elsif  then
q <= data_in;
end if;
 
end process;
end behavioural;

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Finite State Machines

process ( clock )
type state is ( S0, S1, S2, S3.. );
variable current_state, next_state : state;
begin
wait until ( clock = '1' and not( clock'stable ));
case current_state
when S0         =>    next_state := S1;
when S1         =>    next_state := S2;
when S2         =>    next_state := S3;
end case;
current_state <= next_state;
end process,

Preserving Structure - Signals, Components

New IEEE 1076.3 Numeric Support Packages

Numeric_bit
 Based on Built-In Type Bit
Numeric_std
• Two SubTypes Closely Related to Std_Logic

• Signed & Unsigned
• Left Most Bit is Most Significant Bit
• Signed is Two's Compliment
  
  
Functions & Operator Overloads
• For Various Combinations of Signed, Unsigned, Integer and Natural
abs
- ( unary )
+, -, *, /
rem, mod
<, <=, >, >=, =, /=
sll slhift_left, srl shift_right
rol rotate_left, ror rotate_right
not and or nand nor xor

• resize
• to_integer
• to_unsigned
• New for '92
• xnor
• Std_Match
• Translations
• To_01